Memory chips are known that employ a double data rate (DDR) communication scheme. Such a memory may be used in any suitable apparatus including, for example, a graphics acceleration system employing one or more graphics chips that send information to and retrieve data from a memory, such as a frame buffer. Memory interface circuits for facilitating a double data rate communication scheme are also known.
With double data rate communication schemes, a DATA signal, STROBE signal and CLOCK signal are used to communicate data to and from a memory such as between a memory and another circuit such as a graphics accelerator, CPU or any other suitable circuit. With double data rate schemes, typically, the memory chip, such as a DDR SDRAM (double data rate synchronous DRAM) typically expects a DATA signal to be sent to the memory chip, from a graphics chip for example, together with a special STROBE signal. Typically, the STROBE signal has the same frequency as the CLOCK signal that is generated by, for example, the graphics chip, or other suitable circuit. The DATA signal is synchronized with the CLOCK signal. The STROBE signal is typically sent so that the strobe pulse occurs in the middle of a DATA signal window. This occurs typically when the graphics chip is sending data to the memory. Accordingly, the STROBE signal is typically sent later by a quarter of the clock period compared to the DATA signal. This offset allows input memory flip flops to receive the data.
In receiving mode, when the graphics chip or other circuit is receiving data from memory, the memory chip generates and sends the STROBE and DATA signals back. However, typical double data rate interface requirements require the memory chip to send the STROBE and DATA signals simultaneously to simplify the on board memory chip circuitry. Accordingly, a receiving circuit, such as a graphics chip or other suitable circuit, has to delay internally, the received STROBE signal that was sent from the memory chip to provide the same conditions for the receiving circuit input flip flop as for the sending circuits. In other words, the received STROBE signal that is actually the clock input of the graphics chip flip flop has to be in the middle of the data signal window. This time offset has to be stable, including over temperature changes, voltage changes and fabrication process variations.
One approach to providing a requisite delay in the receiving circuit includes a delay circuit that uses several inverters to delay the STROBE signal. The time delay can be adjusted to be a quarter of the clock period (according to typical DDR interface requirements, the data signal has to be received at the rising and falling edge of the STROBE signal). However, in the case where the time delay is temperature, voltage or process dependent, a variable delay in the offset STROBE signal can occur. This can result in loss of data.
For example, FIG. 1 is a diagrammatic illustration of one example of a signal phase shifting circuit 10 that suitably phase shifts a received input signal 12, such as a received STROBE signal, back, for example, a quarter of a CLOCK period so that received data 14 is suitably latched by a latch circuit 16 before the data is passed to core logic 18. A reference signal 20, such as the CLOCK signal, is received by a reference signal period dividing circuit 22. The reference signal period dividing circuit 22 provides a delay control signal 26 that is a voltage controlled delay control signal, to a variable delay circuit 28.
The reference signal period dividing circuit 22 is configured as a type of DLL (delay lock loop). The DLL consists of a phase frequency detector 30, a low pass filter 32, a charge pump 34 and a voltage controlled delay line 37 having several serially connected voltage controlled buffers 36a–36n. With this configuration the propagation time delay between the input of the voltage control delay line 37 and the output of the voltage control delay line 37 is equal to the clock period. The DLL 22 operates, as known in the art, with internal negative feedback. If the reference clock period is not changing, then the DLL will provide synchronization within a reasonable temperature, voltage and fabrication process variation. The phase detector 30 will change the delay control voltage 26 of the voltage control delay line 37 to provide a change any time the clock period time delay between the input of the VCDL 37 and its output is more than one clock period. The delay control voltage will be different with different temperatures, supply voltages or fabrication process variation.
The input signal 12, in this example the STROBE signal, is received by receiver buffer 38 and passed to the variable delay circuit 28 which also employs another voltage control delay line 40 that is commonly controlled by the same delay control signal 26. Since printed circuit board layouts and on chip layouts can add additional delays, the multiplexer 42 and phase shifted output signal drive buffer 44 are used as a delay stage to vary a delay setting of the variable delay circuit 28 to allow selection of delay to compensate for additional printed circuit board layout delays, if desired. A control register 46 is used to control select lines 48 to select the amount of delay required to provide a quarter clock delay or phase shift between the input signal 12 and the shifted signal 50. This allows a type of step control to accurately obtain the requisite STROBE signal in the receiving circuit once the circuit board has been laid out.
As shown, the signal phase shifting circuit 10 can be considered to have a delay lock loop with two voltage control delay lines 40 and 37. Both of them are controlled by the same delay control voltage 26 and they are made of the same delay elements except the voltage control delay line 37 has four times the number of delay elements as the delay line 40. The shorter delay line is used to delay the STROBE signal by a quarter of the memory clock period. Accordingly, since the STROBE signal has the same frequency as the memory clock, and since each STROBE signal represents one valid data cycle, the “quarter delay” will place the STROBE signal in the middle of the data window.
A problem arises since the multiplexer 42 and buffer 44 can shift over temperature and at high frequencies, thereby destabilizing the signal phase shifting required for the STROBE signal.
Another approach may be to have a separate strobe line for every data pad to duplicate the delay chain for every data line. However, a problem can arise due to the phase shift in the STROBE signal and would drastically increase the complexity in fabrication costs of the device. It is desirable to have a constant offset regardless of the supply voltage variations, temperature variations and fabrication process variations.
Accordingly, a need exists for an improved apparatus to facilitate double data rate signaling.